With the development of a chip manufacturing process and improvement in design integration, a problem of chip power consumption becomes an issue that needs to be solved urgently. Besides conventional technologies such as clock gating for reducing the chip power consumption, an adaptive voltage scaling (AVS, Adaptive Voltage Scaling) technology draws much attention as a new effective and important low power consumption technology. Determining a lowest working voltage of a chip is a core step for implementing the AVS technology, where the lowest working voltage needs to guarantee security at the worst working condition of a system. An actual working voltage of the chip may be obtained by adding a proper voltage margin on a basis of the lowest working voltage of the chip. In an AVS system implemented by using the foregoing method, an actual working voltage of the AVS system may reduce to 85% of a working voltage in a condition in which the AVS system is not used, and the power consumption may save up to 30%.
However, when determining the lowest working voltage of the chip, it is very difficult to construct a reasonable test vector, and it is often difficult to ensure that all the related paths are covered. At present, a common practice in the industry is using a design for test (Design For Test, DFT) vector to perform a test, and then determine the lowest working voltage of the chip. Then, comparison with an actual measurement result is made, and a value of the lowest working voltage is revised on this basis. The foregoing method requires a great number of chips for test, a heavy workload, and a time-consuming test procedure.